1. Technical Field
The present invention relates to ferroelectric memory devices.
2. Related Art
In a ferroelectric memory device, a potential appearing on a hit line at the time of normal reading becomes a potential that is voltage-divided by a ferroelectric capacitor and a bit line capacitance. Accordingly, to widen the potential difference of a bit line to secure a sufficient sensing margin, the bit line capacitance is required to be reduced.
As a method to reduce the bit line capacitance, for example, a hierarchized bit line method is known. For example, Japanese laid-open patent application JP-A-2001-167591 describes an example of related art. In the hierarchized bit line method, a plurality of local bit lines, each being connected to a predetermined number of memory cells, is associated with each of main bit lines, and transfer gates that can connect the main bit line and the local bit lines are controlled, whereby any of the local bit lines associated with selected ones of the memory cells is connected to the main bit line. By this method, the junction capacitance of memory cells on the main bit line can be reduced.
However, according to a conventional device structure, when the device structure is miniaturized, an inter-wiring capacitance of adjacent ones of the bit lines greatly influences as a bit line capacitance, such that the bit line capacitance may not be sufficiently reduced. Also, the sensing margin might be deteriorated by noise interference.